000			01011nam a2200157Ia 4500
008			140211s9999 xx 000 0 und d
020			_a9783540959489
100			_aSvensson, Lars.
245			_aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
245			_b18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers /
245			_cedited by Lars Svensson, José Monteiro.
300			_aOn-campus e-Book by Springer under Digital Library Program of Higher Education Commission (HEC) of Pakistan
650			_aComputer science.; Memory management (Computer science).; Logic design.; Computer system performance.; Systems engineering.; Computer Science.; Logic Design.; Processor Architectures.; System Performance and Evaluation.; Arithmetic and Logic Structures.; Memory Structures.; Circuits and Systems.
856	4	1	_3Click her to access the e-Book _uhttp://dx.doi.org/10.1007/978-3-540-95948-9
942			_cEB
999			_c116492 _d116492